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x t august 1998 i 2 c is a licensed trademark of philips electronics n.v. windows is a registered trademark of microsoft corporation. american micr osystems, inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 8.19.98 )6 , & ? 'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 1.0 features triple phase-locked loop (pll) device provides exact ratiometric derivation of audio, processor, and utility clocks i 2 c ? -bus interface for audio and utility clock frequency selection i 2 c ? -bus/board programmable processor clock frequency selection on-chip tunable voltage-controlled crystal oscillator (vcxo) allows precise system frequency tuning tunable audio clock frequencies for undetectable resynchronization of audio and video streams custom frequency selections available - contact your local ami sales representative for more information figure 1: block diagram vcxo i 2 c-bus interface sda scl addr fs6012 uclk processor clock pll audio clock pll utility clock pll xout xin clk_27 aclk pclk xtune psel1 psel0 2.0 description the FS6012-02 is a monolithic cmos clock generator ic designed to minimize cost and component count in digital video/audio systems. at the core of the FS6012-02 is circuitry that implements a voltage controllable crystal oscillator when an external resonator is attached. the circuitry allows device fre- quencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. three high-resolution phase-locked loops independently generate three other selectable frequencies derived from the vcxo frequency. these clock frequencies are re- lated to the vcxo frequency and to each other by exact ratios. the locking of all the output frequencies together can eliminate unpredictable artifacts in video systems and reduces electromagnetic interference (emi) due to frequency harmonic stacking. figure 2: pin configuration 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 scl sda addr vss xin xout xtune vdd psel1 psel0 vss pclk uclk vdd aclk clk27 fs6012 16-pin (0.150) soic
x t august 1998 2 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 1: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin type name description 1 di scl serial data clock 2 dio sda serial data input/output 3di d addr address select bit 4 p vss ground 5 ai xin vcxo feedback 6 ao xout vcxo drive 7 ai xtune vcxo tune 8 p vdd power supply (+5v) 9di d psel1 pclk select msb 10 di d psel0 pclk select lsb 11 p vss ground 12 do pclk processor clock output 13 do uclk utility clock output 14 p vdd power supply (+5v) 15 do aclk audio clock output 16 do clk27 reference clock output 3.0 functional block description 3.1 phase-locked loops each one of the three on-chip plls in the fs6012 is a standard frequency- and phase-locked loop architecture. each pll multiplies the reference oscillator to the desired frequency by a ratio of integers. the frequency multipli- cation is exact. an onboard rom contains the pll settings that control the relationship between reference and output frequen- cies. the i 2 c-bus communications are used to choose a desired rom setting. custom frequency selections are available for this device. contact your local ami sales representative for more information 3.2 output tristate control all four clock outputs of the fs6012 may be tristated to facilitate circuit board testing. to place the outputs in tristate mode, follow this sequence: 1. force xin low (i.e. ground) 2. apply power to the device 3. wait until the internal power-on reset has de-asserted 4. apply a negative-going transition to the psel0 pin outputs may be re-enabled by removing and reapplying vdd to the device. to re-enable outputs without remov- ing power, apply a positive-going transition to the xin in and follow it with a negative-going transition on the psel0 pin.
x t august 1998 3 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 3.3 voltage-controlled crystal oscillator (vcxo) the vcxo provides a tunable, low-jitter frequency refer- ence for the rest of the fs6012 system components. loading capacitance for the crystal is internal to the fs6012. no external components (other than the reso- nator itself) are required for operation of the vcxo. the resonator loading capacitance is adjustable under register control. this permits factory coarse tuning of in- expensive resonators to the necessary precision for digi- tal video applications. continuous fine-tuning of the vcxo frequency is accom- plished by varying the voltage on the xtune pin. the total change (from one extreme to the other) in effective loading capacitance is 1.5pf nominal. the oscillator operates the crystal resonator in the paral- lel-resonant mode. crystal warping, or the pulling of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. the actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. specifically, the motional capacitance of the crystal (usu- ally referred to by crystal manufacturers as c 1 ), the static capacitance of the crystal (c 0 ), and the load capacitance (c l ) of the oscillator determine the warping capability of the crystal in the oscillator circuit. a simple formula to obtain the warping capability of a crystal oscillator is: () ()() c c c c c c c ppm f l l l l 1 0 2 0 6 1 2 1 2 10 ) ( + + - = d where c l1 and c l2 are the two extremes of the applied load capacitance. a crystal with the following parameters is used. with c 1 = 0.02pf, c 0 = 5pf, c l1 = 10pf, c l2 = 22.66pf, the coarse tuning range is: () ()() ppm f 305 10 5 66 . 22 5 2 10 10 66 . 22 02 . 0 6 = + + - = d 4.0 programming information table 2: register summary bit d[x] register bit description 0 aclk select (lsb) 1 aclk select 2 aclk select 3 aclk select (msb) 4 uclk select (lsb) 5 uclk select 6 uclk select 7 uclk select (msb) 8 pclk select (lsb) 9 pclk select 10 pclk select (msb) 11 crystal oscillator coarse tune (lsb) 12 crystal oscillator coarse tune 13 crystal oscillator coarse tune 14 crystal oscillator coarse tune (msb) vcxo fine tune enable/disable bit = 0 disable fine tune 15 bit = 1 enable fine tune
x t august 1998 4 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 4.1 audio pll clock frequencies (aclk) the aclk frequency is controlled by register bits d[0], d[1], d[2], and d[3], accessed via the serial interface. aclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 3: aclk frequency select via i 2 c-bus d[3] d[2] d[1] d[0] pll divider ratio aclk (mhz) 0 0 0 0 32 / 27 32.0000 0 0 0 1 784 / 1875 11.2896 0 0 1 0 512 / 1875 7.3728 0 0 1 1 128 / 1875 1.8432 0 1 0 0 8 / 9 24.0000 0 1 0 1 1 27.0000 0 1 1 0 823 / 1968 11.2912 0 1 1 1 461 / 1688 7.3738 1 0 0 0 99 / 1450 1.8434 1 0 0 1 809 / 910 24.0033 1010 to 1111 duplicate of 0010 to 0111 selections note: contact ami for custom pll frequencies 4.2 utility pll clock frequencies (uclk) the uclk frequency is controlled by register bits d[4], d[5], d[6] and d[7], accessed via the serial interface. uclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 4: uclk frequency select via i 2 c-bus d[7] d[6] d[5] d[4] pll divider ratio uclk (mhz) 0 0 0 0 32 / 27 32.0000 0 0 0 1 34 / 143 6.4196 0 0 1 0 68 / 143 12.8392 0 0 1 1 488 / 2025 6.5067 0 1 0 0 976 / 2025 13.0133 0 1 0 1 13 / 54 6.5000 0 1 1 0 13 / 27 13.0000 0 1 1 1 10 / 11 24.5454 1 0 0 0 1 27.0000 1 0 0 1 10 / 33 8.1818 1010 to 1111 duplicate of 0010 to 0111 selections note: contact ami for custom pll frequencies 4.3 processor pll frequencies (pclk) the pclk frequency is controlled by either the logic lev- els on the psel inputs or through bits d[10:8]. pclk fre- quencies listed below are derived via the pll divider ra- tio from a reference frequency of 27mhz. these inputs have weak pull-downs. table 5: pclk frequency select via pins addr psel1 psel0 pll divider ratio pclk (mhz) 0 0 0 35 / 66 14.31818 0 0 1 423 / 644 17.73447 0 1 0 35 / 264 3.579545 0 1 1 see table 6 1 0 0 427 / 2600 4.43423 1 0 1 423 / 2576 4.433618 1 1 0 1135 / 6912 4.4335937 1 1 1 see table 6 note: contact ami for custom pll frequencies for the special case where both psel inputs are high, the pclk frequency is controlled by data bits d[10:8]. pclk frequencies listed below are derived via the pll divider ratio from a reference frequency of 27mhz. table 6: pclk frequency select via i 2 c-bus d[10] d[9] d[8] pll divider ratio pclk (mhz) 0 0 0 35 / 66 14.3182 0 0 1 423 / 644 17.7345 0 1 0 35 / 264 3.5795 0 1 1 728 / 375 52.4160 1 0 0 427 / 2600 4.4342 1 0 1 423 / 2576 4.43361 1 1 0 1135 / 6912 4.43359 1 1 1 18 / 25 19.4400 note: contact ami for custom pll frequencies
x t august 1998 5 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 4.4 vcxo coarse tuning and enable the vcxo may be coarse tuned by a programmable ad- justment of the crystal load capacitance via d[14:11]. the actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. the vcxo tuning capacitance includes an external load capacitance of 6pf (12pf from the xin pin to ground and 12pf from the xout pin to ground). the fine tuning capability of the vcxo can be enabled by setting d[15] to a logic-one or disabled by clearing the bit to a logic-zero. table 7: vcxo coarse tuning via i 2 c-bus d[14] d[13] d[12] d[11] vcxo tuning capacitance (pf) 0 0 0 0 10.00 0 0 0 1 10.84 0 0 1 0 11.69 0 0 1 1 12.53 0 1 0 0 13.38 0 1 0 1 14.22 0 1 1 0 15.06 0 1 1 1 15.91 1 0 0 0 16.75 1 0 0 1 17.59 1 0 1 0 18.43 1 0 1 1 19.28 1 1 0 0 20.13 1 1 0 1 20.97 1 1 1 0 21.81 1 1 1 1 22.66 4.5 vcxo range figure 3 shows the typical effect of the coarse and fine tuning mechanisms. the difference in vcxo frequency in parts-per-million (ppm) is shown as the fine tuning volt- age on the xtune pin varies from 0v to 5v. the coarse tune range as shown is about 350ppm. as the crystal load capacitance is increased (with increasing coarse tune setting) the frequency is pulled somewhat less with each coarse step and the fine tuning range decreases. the fine tuning range always overlaps a few coarse tun- ing ranges, eliminating the possibility of holes in the vcxo response. note that different crystal warping char- acteristics will change the scaling on the y-axis, but not the overall characteristic of the curves. figure 3: vcxo range vcxo range (ppm) vs. xtune voltage (v) -200 -150 -100 -50 0 50 100 150 200 0123456789101112131415 coarse tune setting d[11:14] vcxo range (ppm) xtune voltage = 0.0v xtune voltage = 5.0v
x t august 1998 6 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 5.0 i 2 c-bus control interface this device is a read/write slave device meeting all philips i 2 c-bus specifications except a general call. the bus has to be controlled by a master device that generates the serial clock scl, controls bus access, and generates the start and stop conditions while the device works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. a device that sends data onto the bus is defined as the transmitter, and a device re- ceiving data as the receiver. i 2 c-bus logic levels noted herein are based on a percent- age of the power supply (vdd). a logic-one corresponds to a nominal voltage of vdd, while a logic-zero corre- sponds to ground (vss). 5.1 bus conditions data transfer on the bus can only be initiated when the bus is not busy. during the data transfer, the data line (sda) must remain stable whenever the clock line (scl) is high. changes in the data line while the clock line is high will be interpreted by the device as a start or stop condition. the following bus conditions are defined by the i 2 c-bus protocol. 5.1.1 not busy both the data (sda) and clock (scl) lines remain high to indicate the bus is not busy. 5.1.2 start data transfer a high to low transition of the sda line while the scl in- put is high indicates a start condition. all commands to the device must be preceded by a start condition. 5.1.3 stop data transfer a low to high transition of the sda line while scl is held high indicates a stop condition. all commands to the device must be followed by a stop condition. 5.1.4 data valid the state of the sda line represents valid data if the sda line is stable for the duration of the high period of the scl line after a start condition occurs. the data on the sda line must be changed only during the low period of the scl signal. there is one clock pulse per data bit. each data transfer is initiated by a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is determined by the master device, and can continue indefinitely. however, data that is overwritten to the de- vice after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first- overwritten fashion. 5.1.5 acknowledge when addressed, the receiving device is required to gen- erate an acknowledge after each byte is received. the master device must generate an extra clock pulse to co- incide with the acknowledge bit. the acknowledging de- vice must pull the sda line low during the high period of the master acknowledge clock pulse. setup and hold times must be taken into account. the master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. in this case, the slave must leave the sda line high to enable the master to generate a stop condition. 5.2 i 2 c-bus operation all programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital inter- face. the device accepts the following i 2 c commands. 5.2.1 slave address after generating a start condition, the bus master broadcasts a seven-bit slave address followed by a r/w bit. the address of the device is: a6 a5 a4 a3 a2 a1 a0 1011x00 where x is controlled by the logic level at the addr pin. the variable addr bit allows two different devices to exist on the same bus. note that every device on an i 2 c- bus must have a unique address to avoid bus conflicts. 5.2.2 random register write procedure random write operations allow the master to directly write to any register. to initiate a write procedure, the r/w bit that is transmitted after the seven-bit device ad- dress is a logic-low. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is written into the slaves address pointer. fol- lowing an acknowledge by the slave, the master is al- lowed to write eight bits of data into the addressed regis-
x t august 1998 7 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 ter. a final acknowledge is returned by the device, and the master generates a stop condition. if either a stop or a repeated start condition occurs during a register write, the data that has been trans- ferred is ignored. 5.2.3 random register read procedure random read operations allow the master to directly read from any register. to perform a read procedure, the r/w bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. this indi- cates to the addressed slave device that a register ad- dress will follow after the slave device acknowledges its device address. the register address is then written into the slaves address pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slaves address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits the eight-bit word. the master does not acknowledge the transfer but does generate a stop condition. 5.2.4 sequential register write procedure sequential write operations allow the master to write to each register in order. the register pointer is automati- cally incremented after each write. this procedure is more efficient than the random register write if several registers must be written. to initiate a write procedure, the r/w bit that is transmit- ted after the seven-bit device address is a logic-low. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is written into the slaves address pointer. following an acknowledge by the slave, the master is allowed to write up to eight bytes of data into the addressed register before the register ad- dress pointer overflows back to the beginning address. an acknowledge by the device between each byte of data must occur before the next data byte is sent. 5.2.5 sequential register read procedure sequential read operations allow the master to read from each register in order. the register pointer is automati- cally incremented by one after each read. this procedure is more efficient than the random register read if sev- eral registers must be read from. to perform a read procedure, the r/w bit that is trans- mitted after the seven-bit address is a logic-low, as in the register write procedure. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the reg- ister address is then written into the slaves address pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slaves address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. the register address pointer will overflow if the initial register address is larger than zero. after the last byte of data, the master does not acknowledge the transfer but does generate a stop condition.
x t august 1998 8 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 figure 4: random register write procedure a a data w a from bus host to device s register address p from device to bus host device address register address acknowledge stop condition data acknowledge acknowledge start command write command 7-bit receive device address figure 5: random register read procedure a r a a a w s register address p s device address start command write command acknowledge register address acknowledge read command acknowledge data no acknowledge stop condition from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address data repeat start figure 6: sequential register write procedure a a a w s p start command write command acknowledge register address acknowledge data data acknowledge data stop command acknowledge acknowledge from bus host to device from device to bus host 7-bit receive device address device address a a register address data data data figure 7: sequential register read procedure a w s start command write command acknowledge register address acknowledge data acknowledge data stop command acknowledge read command no acknowledge from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address a a register address a r a p s device address data data repeat start
x t august 1998 9 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 6.0 electrical specifications table 8: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 9: operating conditions parameter symbol conditions/description min. typ. max. units supply voltage v dd 5v 10% 4.5 5 5.5 v ambient operating temperature range t a 070c resonator or crystal frequency f xin 24 27 28 mhz resonator motional capacitance c mot at cut 25 ff output load capacitance c l 15 pf i 2 c data transfer rate standard mode 100 400 khz
x t august 1998 10 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 10: dc electrical specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic, with loaded outputs i dd f clk = 27mhz; c l ? 15pf 58 80 ma supply current, static i ddl f xin = 0 25 ma vcxo range assumes 6pf load capacitance (12pf from both xin and xout to ground) 350 ppm serial communication i/o (sda, scl) high-level input voltage v ih 0.7v dd v dd +0.3 v low-level input voltage v il v ss -0.3 0.3v dd v hysteresis voltage v hys 0.4v dd v input leakage current i i -1 1 m a low-level output sink current (sda) i ol v ol = 0.4v, v dd = 4.5v 10 25 ma control inputs (addr, psel0, psel1) high-level input voltage v ih 2.4 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current (pull-down) i ih v ih = v dd = 5.5v 5 12.7 50 m a low-level input current i il -1 1 m a crystal oscillator feedback (xin) threshold bias voltage * v th 0.5v dd v input leakage current i i -1 1 m a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout; vcxo tuning disabled 10 pf input loading capacitance * c l(xin) as seen by an external clock driver on xin; xout unconnected; vcxo disabled 20 pf crystal oscillator drive (xout) v o = 0v; d[15] = 0 -45 high-level output source current * i oh v o = 0v, v(xtune) = 5v; d[15] = 1 -52 m a v o = 5v; d[15] = 0 53 low-level output sink current * i ol v o = 5v, v(xtune) = 5v; d[15] = 1 63 m a vcxo tuning input (xtune) input leakage current i i -1 1 m a clock outputs (aclk, clk27, pclk, uclk) high-level output source current i oh v o = 2.4v -46 ma low-level output sink current i ol v o = 0.4v 64 ma z oh v o = 0.5v dd ; output driving high 53 output impedance z ol v o = 0.5v dd ; output driving low 57 w tristate output current i oz -10 +10 m a short circuit source current * i osh v o = 0v; shorted for 30s, max. -60 ma short circuit sink current * i osl v o = 5v; shorted for 30s, max. 65 ma
x t august 1998 11 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 11: ac timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (pclk) 14.318 48 52 17.734 48 52 3.579 48 52 52.416 40 44 4.4342 48 52 4.4336 48 52 4.4335 48 52 duty cycle * from rising edge to rising edge at 2.5v 19.440 48 52 % 14 .3 18 8 0 0 17.734 1410 3.579 870 52.416 980 4.4342 1070 4.4336 1300 4.4335 1630 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 19.440 1430 ps 14.318 510 17.734 500 3.579 520 52.416 620 4.4342 680 4.4336 750 4.4335 740 jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 19.440 580 ps clock stabilization * t stb output active from power-up 960 m s rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.5 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 1.8 ns clock output (clk27) duty cycle * crystal oscillator frequency out, from rising edge to rising edge at 2.5v 27 45 48 % clock stabilization time * t stb output active from power-up 300 m s rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.5 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.2 ns
x t august 1998 12 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 12: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (aclk) 32.0000 44 48 11.2896 48 52 7.3728 48 52 1.8432 48 52 24.0000 44 48 27.0000 44 48 11.2912 48 52 7.3738 48 52 1.8434 48 52 duty cycle * from rising edge to rising edge at 2.5v 24.0033 44 48 % 32.0000 1700 11.2896 510 7.3728 600 1.8432 2360 24.0000 330 27.0000 230 11.2912 520 7.3738 940 1.8434 890 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 24.0033 920 ps 32.0000 440 11.2896 670 7.3728 600 1.8432 750 24.0000 510 27.0000 1660 11.2912 680 7.3738 560 1.8434 710 jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 24.0033 600 ps clock stabilization time * t stb output active from power-up 770 m s rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.5 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 1.8 ns
x t august 1998 13 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 13: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (uclk) 32.0000 44 48 6.4196 48 52 12.8392 48 52 6.5067 48 52 13.0133 48 52 6.5000 48 52 13.0000 48 52 24.5454 45 49 27.0000 44 48 duty cycle * from rising edge to rising edge at 2.5v 8.1818 48 52 % 32.0000 1380 6.4196 850 12.8392 810 6.5067 880 13.0133 870 6.5000 660 13.0000 930 24.5454 770 27.0000 380 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 8.1818 720 ps 32.0000 470 6.4196 470 12.8392 510 6.5067 620 13.0133 620 6.5000 650 13.0000 550 24.5454 550 27.0000 1940 jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 8.1818 610 ps clock stabilization time * t stb output active from power-up 600 m s rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.6 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.0 ns
x t august 1998 14 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 14: serial interface timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. min and max characterization data are 3 s from typical. standard mode parameter symbol conditions/description min. max. units clock frequency f scl scl 0 100 khz bus free time between stop and start t buf 4.7 m s set up time, start (repeated) t su:sta 4.7 m s hold time, start t hd:sta 4.0 m s set up time, data input t su:dat sda 250 ns hold time, data input t hd:dat sda 0 m s output data valid from clock t aa minimum delay to bridge undefined region of the fall-ing edge of scl to avoid unintended start or stop 3.5 m s rise time, data and clock t r sda, scl 1000 ns fall time, data and clock t f sda, scl 300 ns high time, clock t hi scl 4.0 m s low time, clock t lo scl 4.7 m s set up time, stop t su:sto 4.0 m s figure 8: bus timing data scl sda ~ ~ ~ ~ ~ ~ stop t su:sto t hd:sta start t su:sta address or data valid data can change figure 9: data transfer sequence scl sda in t hd:dat ~ ~ t hd:sta t su:sta t su:sto t lo t hi sda out t su:dat ~ ~ ~ ~ t buf t r t f t aa t aa
x t august 1998 15 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 7.0 package information table 15: 16-pin soic (0.150") package dimensions dimensions inches millimeters min. max. min. max. a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 q 0 8 0 8 be d a 1 seating plane h e 16 1 all radii: 0.005" to 0.01" base plane a 2 c l q 7 typ. h x 45 a x t r table 16: 16-pin soic (0.150") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 108 c/w corner lead 4.0 lead inductance, self l 11 center lead 3.0 nh lead inductance, mutual l 12 any lead to any adjacent lead 0.4 nh lead capacitance, bulk c 11 any lead to v ss 0.5 pf
x t august 1998 16 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 8.0 ordering information ordering code device number font package type operating temperature range shipping configuration 11212-002 fs6012 -02 16-pin (0.150) soic (small outline package) 0 c to 70 c (commercial) tubes purchase of i 2 c components of american microsystems, inc., or one of its sublicensed associated compa- nies conveys a license under philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. copyright ? 1998 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami reserves the right to discontinue production and change specifications and prices at any time and without notice. amis products are intended for use in commercial applications. applications requiring ex- tended temperature range, unusual environmental requirements, or high reliability applications, such as military, medi- cal life-support or life-sustaining equipment, are specifically not recommended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: t g p@amis.com
x t august 1998 17 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 9.0 demonstration board schematic a simple demonstration board and dos-based software is available from american microsystems that illustrates the capabilities of the FS6012-02. the board schematic is shown below. components listed with an asterisk (*) are not required in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. a cabled interface between a computer parallel port (db25 connector) and the board (j1) is provided. contact your local sales representative or the company directly for more information. fs6012 scl sda addr gnd xin xout xtune vdd clk27 aclk vdd uclk pclk gnd psel0 psel1 rp1 1k c1 2.2f c3 0.1f r3* 100 r2* 100 r1* 100 r5* 100 r4* 100 r6 10 r7 10 c2 2.2f c4 0.1f y1 27mhz aclk clk27 uclk pclk psel1 psel0 scl sda addr c5* 100pf +5v +5v 5 4 1 2 3 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 jp2 jp1 +5v j1* 6 +5v +5v gnd r8* 47 r9* 47 r10* 47 r11* 47 c6 12pf c7 12pf
x t august 1998 18 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 9.1 contents demonstration board interface cable (db25 to 6-pin connector) data sheet self-uncompressing exe file containing demonstration software, including: - install.bat 0.73kb - fs6012.bat 0.24kb - fs6012t.bas 12.96kb 9.2 requirements pc running ms-dos or ms windows 3.1x, with accessible parallel (lpt1) port ms-qbasic v. 1.1 or later (or equivalent software) 13.9kb available free space on drive c: 9.3 board setup and software installa- tion instructions 1. at the appropriate disk drive prompt (a:\) type install to automatically copy demo files to the c: drive. note: this demo software requires microsoft qba- sic or equivalent to run. make sure the directory containing qbasic.exe is in the dos path statement, or move the demo files to a directory containing ba- sic. 2. connect a +5 volt power supply to the board: red = +5v, black = ground. 3. remove all software keys from the computer parallel port. 4. connect the supplied interface cable to the parallel port (db25 connector) and to the demo board (6-pin connector). make sure the cable is facing away from the board C pin 1 is the red wire. 5. connect the clock outputs to the target application board with a twisted-pair cable. 9.4 demo program 1. type fs6012 at the c:\fs6012 prompt to run the qbasic-based demo program. 2. the following heading banner should appear: figure 10: banner ********************************************** * * * fs6012 utility program * * * * press any key to continue..... * * * ********************************************** 3. after pressing any key, a menu should appear con- taining a list of the program hot keys, a message that the computer parallel (lpt1) port was found, and the address at which the port was found. figure 11: menu *********************** * fs6012 utility * * * * (r)ead * * (w)rite * * (v)cxo coarse set * * (a)clk set * * (u)clk set * * (p)clk set * * (e)nable vcxo * * (s)et psel strap * * addrse(l) strap set * * e(x)it * **** power is on ***** refer to table 17 for a description of each hot key. 4. to change the frequency of the desired clock, press the appropriate hot key. the keys are not case sensi- tive. refer to table 3 for aclk frequencies, table 4 for uclk frequencies, table 6 for pclk frequencies. refer to table 7 for the vcxo coarse tune bits. 5. data is sent to the device in a two-byte sequence, referred to as address 0 and address 1. the address 0 byte contains bits 0 to 7 (see table 2) and the ad- dress 1 byte contains bits 8-15. during a read/write operation, data is displayed in the following format: read of address {0 or 1} is {data in decimal(data in hex)} writing {data in decimal(data in hex)} to address {0 or 1}
x t august 1998 19 8.19.98 )6 , &'ljlwdo9lghr$xglr&orfn*hqhudwru,& ,62 table 17: hot key description command key bits address range description 0-7 0 read r 8-15 1 - manual read with selectable address 0-7 0 write w 8-15 1 all 15 bits manual write with selectable address and user-defined data aclk a 0-3 0 0000- 1111 cycles through aclk frequencies (table 3) uclk u 4-7 0 0000- 1111 cycles through uclk frequencies (table 4) pclk p 8-10 1 000-111 cycles through pclk frequencies (table 6) vcxo course set v 11-14 1 0000- 1111 digital coarse tune of the vcxo vcxo enable e15 1 0-1 enables fine tune of the vcxo via the xtune pin set psel strap s - - 00-11 cycles through pclk frequencies via psel0 and psel1 pins (table 5) address select strap l- - 0-1 alters addr bit in the i 2 c address exit x - - - exits the demo program 6. observe the response to the hot key selection. re- peated pressing of the same key will scroll through the entire range of settings for the selected com- mand, returning to the initial setting. 7. the read and write commands permit the user to read data from a desired register or to manually over- write data into a desired register. 8. pressing a hot key strobes a 15-bit message to the demo board via the interface cable. an example of the response to the key selection is shown below: reading... read of address 0 is 22(0x16) read done... writing 17(0x11) to address 0 write done... 9. the set psel strap and addrsel strap set com- mands drive pins 3, 4 and 5 (addr, psel0, and psel1) directly. no read/write activity will be ob- served on the screen. 10. the fs6012 uses i 2 c-bus communication. the in- terface cable must be correctly attached to the demo board prior to performing any functions or an error message will be displayed. figure 12: error messages *********************************************** * * * warning !! - i2c byte send ack failed !!! * * * * (press any key to continue) * * * *********************************************** during a write procedure (from the computer to the de- vice), an acknowledge bit should be returned by the de- vice. the above error occurs if the computer fails to re- ceive an acknowledge from the device. *********************************************** * * * warning !! - i2c control ack failed !!! * * * * (press any key to continue) * * * *********************************************** the state of the i 2 c-bus is checked by the software dur- ing a sequential register read to the device. the above message is displayed if the i 2 c-bus has a one-conflict when the acknowledge was supposed to occur. *********************************************** * * * warning !! - i2c write of 1 failed !!! * * * * (press any key to continue) * * * *********************************************** the state of the i 2 c-bus is checked by the software dur- ing the transfer of information to the device. the above message is displayed if the i 2 c-bus has a data bit zero- conflict when the bit was supposed to be a one.
x t august 1998 20 8.19.98 )6 , &'l j lwdo9lghr$xglr&orfn*hqhudwru,& ,62 *********************************************** * * * warning !! - i2c write of 0 failed !!! * * * * (press any key to continue) * * * *********************************************** the state of the i 2 c-bus is checked by the software dur- ing the transfer of information to the device. the above message is displayed if the i 2 c-bus has a data bit one- conflict when the bit was supposed to be a zero. *********************************************** * * * warning !! - i2c bus not in active state !! * * * * (press any key to continue) * * * *********************************************** the state of the i 2 c-bus is checked by the software just before a stop command is given to the device. the above message is displayed if the i 2 c-bus has inadver- tently become idle (before the stop command is given) when it is supposed to be active. ********************************************* * * * warning !! - i2c bus not in idle state !! * * * * (press any key to continue) * * * ********************************************* the state of the i 2 c-bus is checked by the software just after a stop command is given to the device. the above message is displayed if the i 2 c-bus has not become idle (after the stop command is given). ******************************************* * warning !! - hardware error detected !! * ******************************************* this error occurs if i 2 c communication cannot be estab- lished with the device. table 18: cable interface color j1 db25 signal red 1 2 scl white 2 16 sda green 3 8 addr blue 4 5 psel1 brown 5 4 psel0 black 6 25 gnd figure 13: board silkscreen figure 14: board traces - component side left right figure 15: board traces - solder side right left

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